1. Field of the Invention
The present invention relates to an integrated circuit that includes a high-speed serial interface with clock generation capabilities. More particularly, the high-speed serial interface includes a high-frequency timing reference generator that can act as a timing source for the integrated circuit.
2. Relevant Background
Integrated circuits take functions that were previously provided by separate chips and integrate them into a single chip. The natural evolution of integrated circuits has lead to System On Chip (xe2x80x9cSOCxe2x80x9d) circuits that integrate most system functions on a single IC chip. SOCs also typically include one or more internal timing references that provide clocking and timing information for the synchronous core logic and macrocells in the chip.
An example of an SOC in use today is a disk drive SOC that has a digital signal processor (xe2x80x9cDSPxe2x80x9d), memory, data path controller, data interface, macrocells, and DSP peripherals on a single IC chip. Disk drive SOCs commonly have a parallel data interface and typically include a quartz crystal or ceramic resonator incorporated into the feedback of an oscillator circuit to provide a stable frequency timing reference. The timing reference frequency of the stable frequency timing reference is usually low (e.g., 30 MHz) when compared with the high frequencies that are typical for the core logic and macrocells of the SOC (e.g., hundreds of megahertz or more). The high frequencies are typically generated by processing the signal from the stable frequency timing reference with Phase Locked Loop (xe2x80x9cPLLxe2x80x9d) macrocells and programmable dividers.
PLLs typically multiply up the frequency of the lower frequency timing reference in a ratio that is defined by forward and feedback dividers (i.e., circuit logic). PLLs also typically include a phase detector, compensator, and Voltage Controlled Oscillator (xe2x80x9cVCOxe2x80x9d) that are mixed-signal circuits. The high-frequency signals generated by PLLs are typically further manipulated by digital dividers and other circuit logic to produce signals with frequencies needed by the core logic and macrocells in an SOC.
The PLLs and programmable dividers, which are typically provided as a macrocell in a SOC, are optimized around the particular stable frequency timing reference used with the SOC. These mixed-signal macrocells have both analog and digital circuitry and therefore require both analog and digital design methods for implementation. Thus, development of these high-frequency, mixed-signal macrocells require more development time and resources than all digital circuits that designers can synthesize with high-level programming languages, and do have to know details of chip fabrication techniques.
Some recent SOCs designs substitute or complement a parallel data interface with a high-speed serial interface. The high-speed serial interface typically includes an oscillator to provide a stable frequency timing reference, and a dedicated high-quality, high-frequency timing reference generator that is dedicated for use in the serial interface macrocell circuitry. Unfortunately, because the high-frequency timing reference generator is only used by the serial interface, other SOC circuitry develop timing reference signals from the oscillator using mixed-signal circuitry in a substantially conventional manner. Hence, these high-speed serial interface SOCs also include PLLs and programmable dividers that require the designer to spend time and resources optimizing these and other components as well as implementing design changes. A need exists for systems and techniques that eliminate or simplify the requirements for mixed-signal timing reference generator circuitry and preferably leverage timing reference generation components already incorporated in the serial interface circuitry and macrocells.
The present invention includes an integrated circuit comprising a serial interface that includes a timing reference generator, an initial divider in electronic communication with the timing reference generator, and a final divider, fixed or programmable, in electronic communication with the initial divider.
The present invention also includes an integrated circuit comprising a serial ATA (xe2x80x9cSATAxe2x80x9d) interface that includes a timing reference generator and an oscillator (wherein the oscillator is coupled to and in electronic communication with a quartz crystal stable frequency timing reference) an initial divider that is coupled to and in electronic communication with the timing reference generator, and a final divider that is coupled to and in electronic communication with the initial divider, wherein the final divider comprises a portion of the core logic of the integrated circuit (wherein said integrated circuit does not include a phase locked loop macrocell outside of the timing reference generator of the high-speed serial interface).
The present invention further includes a method of generating a timing reference signal in an integrated circuit comprising the steps of generating a high-frequency signal with a timing reference generator that is part of a serial interface within the integrated circuit, dividing the high-frequency signal with an initial divider to generate a mid-frequency timing reference signal, and dividing the mid-frequency timing reference signal with final dividers to generate final timing reference signals.
These and other features and advantages of the invention, as well as the structure and operations of various embodiments of the invention, are described in detail below with reference to the accompanying figures.